A serial data stream may be made up with n channels of serial data. For example, n may be equal to 2m. Each of the n channels is of relatively low speed serial data whereas the serial data stream may be relatively high speed. Each of the n channels has the same data rate. FS is the rate of the bits of the high speed serial data stream whereas FL is the rate of bits of the individual channels. FS and FL are related by FS=FL/n.
The high speed serial data stream may need to be processed to regenerate the original channels. Various solutions have been proposed.
In a first flip-flop based dispatcher, the dispatcher uses n flip-flops synchronized with different clock signals operating at FL but delayed by 2π/n in phase from each other. The first technique requires a lot of control signals (n). The arrangement presents a high input load that increases with n and hence its input delay is relatively large. The area required to implement such an arrangement is relatively high and is also proportional to n. Given that the different flip-flops share the same data input, implementation of such an arrangement may be difficult because of the high wire routing complexity. The circuit is power hungry because of the utilization of flip-flops characterized by relatively high static power consumption. Further, the considerable timing constraints from the hold and setup times of the flip-flops make the arrangement sometimes unsuitable for dispatching high speed serial data streams and consequently it offers a low jitter tolerance.
A second technique uses a tree of 1:2 demultiplexing based flip-flops which form the de-multiplexer. The sampling is done in the middle of the pulse width. This may require phase delaying. The second technique has a serial data input to a first demultiplexer, the output of that multiplexer being input to further de-multiplexers. There are m levels of de-multiplexing until the n channels are separated.
The second technique tends to have high power consumption. In particular, the static power consumption is relatively high due to the number of flip-flops. The dynamic power consumption is also relatively high due to the high frequency control signals and also the number of flip-flops. Furthermore, the area required to implement such a technique tends to be large. In some arrangements, such a circuit may not be able to dispatch high speed serial data streams. Such an arrangement may also have a low jitter tolerance.
It has been proposed to have a combinatorial logic based dispatcher. This takes the incoming signal and provides an AND function on the incoming signal with a Boolean code to dispatch the data. Such an arrangement tends to have n AND gates with m+1 inputs and m inverters. The Boolean signals are m clocks operating at FS/m and are delayed from each other by 2π/m in phase. These signals can be produced by an incremental counter. Incrementing the counter can be done at the same time as the data changes and it is therefore held stable during one pulse width equal to 1/FS.
Such an arrangement may have a disadvantage that it has a high input load that increases with n. Consequently, the input delay of this arrangement is potentially high. Because of the shared inputs, there may be some routing complexity. Furthermore, some logical effort needs to be applied to design considerations. Such an arrangement can dispatch high speed material data streams but middle sampling of data may not be possible when using signals derived from the control signals.
In another arrangement, a transmission gate based dispatcher arrangement can be provided. A transmission gate type dispatcher has a transmission gate for each channel. Bit switching is done by the transmission gates. A 1:n dispatcher has n transmission gates having a shared input. The output of each transmission gate produces the signals of one channel. Baud rate counter incrementing is used. Such an arrangement may have a disadvantage that it has a high load input load that increases with n and therefore an amplifier may be required. A relatively large number of control signals are required which require the using of an m to n decoder to reduce the number of these signals.